The present invention relates generally to flat panel light emitting devices such as flat panel displays, backlights for instrumentation displays, and the like, and more specifically to a flat panel light emitting device such as a flat panel display having an interconnect bump for coupling elements of the display to an interconnect substrate.
Flat panel polymer light emitting diode (PLED) devices are comprised of layers of conjugated, semiconducting polymers sandwiched between electrodes formed on a transparent, insulating glass or plastic substrate. When a current is passed between the electrodes, the molecular structure of the semi-conducting polymer layers is excited, creating light emission.
In one application, PLED devices may be pixilated (i.e., partitioned into picture elements or pixels) to facilitate use of the device as a flat panel display. Typically, in such displays, a PLED pixel web is formed by depositing a first electrode (anode) layer that is divided into a plurality of rows. One or more layers of semi-conducting polymers are then deposited over the first electrode layer. A second electrode (cathode) layer is next formed over the first electrode layer and semi-conducting polymer layers. The second electrode layer is partitioned into a plurality of columns oriented so as to intersect the rows of the first electrode layer. In this manner, the area of intersection of each row and column may define a display element, one or more of which may be grouped to form a pixel of the PLED pixel web. An interconnect substrate is employed to couple the PLED pixel web to a display driver for controlling the operation of pixels within the PLED pixel web.
One problem encountered in the manufacture of flat panel displays employing large PLED pixel webs (i.e., webs having large numbers of pixels) is that the duty cycle of such displays becomes low making the displays inefficient. Segmenting the pixels of the PLED pixel web into rows may reduce this lack of efficiency. Connections may then be made between groups of rows or individual rows and column line segments formed on the interconnect substrate. However, the interconnection of a large PLED pixel web to an interconnect substrate is at present difficult since no efficient interconnect technology exists. Thus, a PLED flat panel display utilizing complex interconnect patterning becomes expensive to manufacture placing it at a cost disadvantage when compared to other display technologies.
Accordingly, the present invention is directed to a method of forming interconnect bumps within the pixel web of a flat panel light emitting device, wherein the interconnect bumps may be utilized to make connections to an interconnect substrate of the flat panel light emitting device.
In accordance with one aspect of the invention, a flat panel display is comprised of a plurality of display elements formed on a transparent, insulating substrate. Interconnect bumps formed in the pixel web operably couple the display elements to an interconnect substrate. In an embodiment of the invention, the pixel web comprises a conjugated polymer light emitting diode (PLED) pixel web of a flat panel display. The PLED pixel web is comprised of layers of conjugated, semiconducting polymers including a hole transport layer (HTL) and an electron transport layer (ETL) formed between first and second electrode layers on an insulating substrate. The interconnect bump is formed beneath the second electrode layer on one of the insulating substrate, the first electrode layer, the hole transport layer (HTL), and the electron transport layer (ETL) for extending the second electrode layer away from the insulating substrate so the second electrode layer may be operably coupled to an interconnect substrate.
In accordance with a further aspect of the invention, a method of forming an interconnect bump in a flat panel display is disclosed. In one embodiment, the method includes the steps of depositing a first electrode layer on a transparent, insulating substrate, forming a bump of photoresist over the insulating substrate, and depositing a second electrode layer over the first electrode layer and the deposited bump wherein the bump extends the second electrode layer away from the insulating substrate so the second electrode layer may be operably coupled to an interconnect substrate. In exemplary embodiments, the method may further include the steps of forming a hole transport layer (HTL) on the first electrode layer and forming an electron transport layer (ETL) on the hole transport layer wherein the bump is formed on one of, the insulating substrate, the first electrode layer, the hole transport layer (HTL), and the electron transport layer (ETL).
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.